Design of Very High-Frequency Multirate Switched-Capacitor by Ben U Seng Pan, Rui Paulo da Silva Martins, Jose de PDF

By Ben U Seng Pan, Rui Paulo da Silva Martins, Jose de Albuquerque Epifanio da Franca

ISBN-10: 0387261214

ISBN-13: 9780387261218

ISBN-10: 0387261222

ISBN-13: 9780387261225

Layout of Very High-Frequency Multirate Switched-Capacitor Circuits provides the speculation and the corresponding CMOS implementation of the unconventional multirate sampled-data analog interpolation strategy which has its nice capability on very high-frequency analog frond-end filtering as a result of its inherent twin benefit of decreasing the rate of data-converters and DSP middle including the specification leisure of the publish continuous-time filtering. this method thoroughly removes the conventional phenomenon of sampled-and-hold frequency-shaping on the reduce enter sampling expense. additionally, so one can take on actual IC imperfections at very excessive frequency, the state of the art circuit layout and format innovations for high-speed Switched-Capacitor (SC) circuits are comprehensively mentioned: -Optimum circuit structure tradeoff analysis-Simple pace and gear trade-off research of lively elements-High-order filtering reaction accuracy with recognize to capacitor-ratio mismatches-Time-interleaved impact with appreciate to realize and offset mismatch-Time-interleaved impact with admire to timing-skew and random jitter with non-uniformly holding-Stage noise research and allocation scheme-Substrate and provide noise reduction-Gain-and offset-compensation techniques-High-bandwidth low-power amplifier layout and layout-Very low timing-skew multiphase iteration tailored optimal layout examples in CMOS are offered. the 1st one achieves a 3-stage 8-fold SC interpolating clear out with 5.5MHz bandwidth and 108MHz output sampling price for a NTSC/PAL CCIR 601 electronic video at three V. one other is a 15-tap 57MHz SC FIR bandpass interpolating filter out with 4-fold sampling price bring up to 320MHz and the first-time embedded frequency band up-translation for DDFS procedure at 2.5V. The corresponding chip prototype achieves thus far the top working frequency, optimum filter out order and optimum middle frequency with optimum dynamic diversity below the bottom provide voltage compared to the formerly mentioned high-frequency SC filters in CMOS.

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Additional info for Design of Very High-Frequency Multirate Switched-Capacitor Circuits: Extending the Boundaries of CMOS Analog Front-End Filtering (The Springer International Series in Engineering and Computer Science)

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1993. Mitra, “Multirate analog-digital systems for signal processing and conversion,” Proc. 1997. Martins, “IIR Switched-Capacitor decimator building blocks with optimum implementation,” IEEE Trans. Circuits and Systems, Vol. 81-90, Jan. 1990. Brisco, “CMOS analog front-end for conversational video phone modem,” in Proc. 4/5, 1989. Dallavalle, “PCM Telephony: Reduced architecture for a D/A converter and filter combination,” IEEE J. Solid-State Circuits, vol. 1990. Palmisano, “Integrated digital modulator and analog front-end for GSM digital cellular mobile radio system,” Proc.

129-134, Jan. 2001. 2001. 2002. 1998. 3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR,” IEEE J. 297-307, Mar. 2000. Lee,"Fractal capacitors," IEEE J. 2035-2041, Dec. 1998. Hajimiri, "Capacity limits and matching properties of integrated capacitors," IEEE J. 384-393, Mar. 2002. Quinn, “High-accuracy charge-redistribution SC video bandpass filter in standard CMOS,” IEEE J. 1998. Moon, “CMOS High-Frequency Switched-Capacitor filters for telecommunication applications,” IEEE J.

Moreover, only one time-shared SC output accumulator with 3 multiplexed summing branches for 3 polyphase subfilters is employed to produce L interpolated outputs. 10]. The total number of opamps will be saved to 4 only and the sensitivity performance will also be improved when compared to those of the canonic realization, thus it is more suitable for lower speed applications. The simulated overall and passband amplitude responses are presented in Figure 2-9. 2 dB rolloff caused by output sampling rate 30 MHz which is much better than nearly 2 dB rolloff suffered from the input S/H distortion in conventional non-optimum-class of SC interpolating filters.

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Design of Very High-Frequency Multirate Switched-Capacitor Circuits: Extending the Boundaries of CMOS Analog Front-End Filtering (The Springer International Series in Engineering and Computer Science) by Ben U Seng Pan, Rui Paulo da Silva Martins, Jose de Albuquerque Epifanio da Franca


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