Download PDF by Angela Krstic, Kwang-Ting (Tim) Cheng: Delay Fault Testing for VLSI Circuits

By Angela Krstic, Kwang-Ting (Tim) Cheng

ISBN-10: 1461375614

ISBN-13: 9781461375616

ISBN-10: 1461555973

ISBN-13: 9781461555971

In the early days of electronic layout, we have been all in favour of the logical correctness of circuits. We knew that if we bogged down the clock sign sufficiently, the circuit might functionality thoroughly. With advancements within the semiconductor approach know-how, our expectancies on velocity have soared. a regularly requested query within the final decade has been how briskly can the clock run. This places major calls for on timing research and hold up checking out. Fueled through the above occasions, an immense development has happened within the study on hold up checking out. contemporary paintings contains fault types, algorithms for try out iteration and fault simulation, and techniques for layout and synthesis for testability. The authors of this publication, Angela Krstic and Tim Cheng, have in my view contributed to this study. Now they do a fair larger carrier to the occupation by means of accumulating the paintings of a giant variety of researchers. as well as expounding this sort of good deal of data, they've got introduced it with utmost readability. To extra the reader's figuring out many key innovations are illustrated by means of easy examples. the elemental rules of hold up checking out have reached a degree of adulthood that makes them compatible for perform. In that feel, this booklet is the easiest x hold up FAULT trying out FOR VLSI CIRCUITS on hand advisor for an engineer designing or trying out VLSI platforms. Tech­ niques for course hold up checking out and to be used of slower attempt apparatus to check high-speed circuits are of specific interest.

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Extra info for Delay Fault Testing for VLSI Circuits

Example text

L Non-robust path. Therefore, non-robust testable paths are also static sensitizable. 6. 6 signal d is the non-robust off-input. If the rising transition on signal d arrives later than the transition on signal c, it will mask the propagation of the falling transition from signal c to signal e. In this case the test shown in the figure will not be able to detect the faulty target path (shown in bold). , a non-robust testable path can have several possible nonrobust tests. These non-robust tests differ in the number and positions of non-robust off-inputs in the given target path.

Let these paths be %, ... qi m • If all paths % + Pi, ... , qi m + Pi, where symbol" +" denotes path concatenation, can be robustly tested and if the circuit passes these tests, it can be guaranteed that the non-robust test for the target path will not be invalidated. The target path delay fault is called a validatable nonrobust path delay fault [129]. The robust tests for the concatenated paths together with the non-robust test V for the target path form a validatable non-robust test. 6. Path {t, ade} is the only path through signal d that can invalidate the non-robust test shown in the figure.

This experiment clearly shows the value and need for delay testing. The studies by Maxwell et ai. [107, 108] considered the detection of timing defects by functional and IDDQ tests. These studies have shown that functional tests applied at-speed and IDDQ tests can detect some, but not all, delay defects. Their experiment [108] analyzed a sample of three wafer lots consisting of 26,415 die (fully static standard cell design with 8,577 gates and 436 flip-flops). The test set consisted offunctional vectors run at slow speed (2 MHz) and at high speeds (20 MHz and 32 MHz), scan tests and IDDQ tests.

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Delay Fault Testing for VLSI Circuits by Angela Krstic, Kwang-Ting (Tim) Cheng


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