Cryptographic Hardware and Embedded Systems - CHES 2013: by Amir Moradi, Oliver Mischke (auth.), Guido Bertoni, PDF

By Amir Moradi, Oliver Mischke (auth.), Guido Bertoni, Jean-Sébastien Coron (eds.)

ISBN-10: 3642403484

ISBN-13: 9783642403484

ISBN-10: 3642403492

ISBN-13: 9783642403491

This booklet constitutes the complaints of the fifteenth foreign Workshop on Cryptographic and Embedded structures, CHES 2013, held in Santa Barbara, CA, united states, in August 2013. The 27 papers awarded have been rigorously reviewed and chosen from 132 submissions. The papers are geared up within the following topical sections: side-channel assaults; actual unclonable functionality; light-weight cryptography; implementations and fault assaults; effective and safe implementations; elliptic curve cryptography; protecting; side-channel assaults and countermeasures.

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Additional info for Cryptographic Hardware and Embedded Systems - CHES 2013: 15th International Workshop, Santa Barbara, CA, USA, August 20-23, 2013. Proceedings

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Tunstall, M. ) InfoSecHiComNet 2011. LNCS, vol. 7011, pp. 128–143. Springer, Heidelberg (2011) 8. : On the problem of the most efficient tests of statistical hypotheses. Philosophical Transactions of the Royal Society of London. Series A, Containing Papers of a Mathematical or Physical Character 231, 289–337 (1933) 9. : On the Exact Success Rate of Side Channel Analysis in the Gaussian Model. , Sica, F. ) SAC 2008. LNCS, vol. 5381, pp. 165–183. Springer, Heidelberg (2009) 10. : An overview of power analysis attacks against field programmable gate arrays.

32 A. Thillard, E. Prouff, and T. Roche Let us illustrate the application of the confidence level with the comparison of the two following rules, corresponding to the criterion described in the preamble of this section: – Rule R0 : output the candidate ranked first at the end of the N − th attack. – Rule Rt : output the candidate ranked first at the end of the N − th attack, only if it was also ranked first for all attacks performed using Nt to N observations. By definition of R0 , and using the notations of Section 2, the confidence associated to R0 satisfies: c(K R0 ) = P(R0 (N ) = 1) = P(R0 (N ) = 1), δ P(Rδ (N ) = 1) which can be computed thanks to Theorem 2.

The DC blocker we used is a BLK-89-S+ from Mini-Circuits and indeed is a high-pass filter which stops frequencies below 100kHz. We also used two different amplifiers, ZFL-1000LN+ from Mini-Circuits and PA303 from Langer EMV-Technik. We made an exemplary design containing only an 8-bit key XOR followed by an unprotected AES S-box. Sequentially we gave two plaintext bytes to this module while after the computation of the XOR and the S-box (in one clock cycle) the circuit is kept idle for 16 clock cycles.

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Cryptographic Hardware and Embedded Systems - CHES 2013: 15th International Workshop, Santa Barbara, CA, USA, August 20-23, 2013. Proceedings by Amir Moradi, Oliver Mischke (auth.), Guido Bertoni, Jean-Sébastien Coron (eds.)


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