By Dr. Ron Ho, Dr. Robert Drost (auth.), Ron Ho, Robert Drost (eds.)
Designers of next-generation high-performance desktops face a bunch of technical demanding situations. For the previous a number of a long time, emerging clock frequencies and elevated chip integration have fueled the expansion of laptop functionality. Now those traits have slowed: energy and complexity constrains extra raises in clock frequencies, and monetary realities restrict the speed of Moore's legislations. Coupled info communique presents a manner ahead, and this ebook, Coupled info conversation options for High-Performance and Low-Power Computing, offers a complete evaluation for such coupled info ideas. Coupled facts communique permits chips to communicate—capacitively or inductively—over brief distances among chips with out solder, and essentially shifts the layout paradigm from single-chip integration to single-package integration. This booklet covers the state of the art within the circuits, architectures, and chip packaging for this novel chip-to-chip conversation know-how and showcases its capability to force the arrival many years of progress. Coupled info verbal exchange innovations for High-Performance and Low-Power Computing can be of curiosity to scholars and architects in circuits and method architecture.
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Extra resources for Coupled Data Communication Techniques for High-Performance and Low-Power Computing
How to package? andPhotonics? ground pads must be scaled accordingly with each technology generation and •Type of interstratal interconnect(s)? ? DC-DC? sized on-chip appropriately wires and decoupling capacitors are allocated for the •How H tto assemble/bond? bl /b d? power distribution network . The above issues are discussed in more detail later •Chip-scale or wafer-scale? in the chapter. ? moreA??? Power delivery is not the only •And challenge. key bottleneck to the realizaHeat removal?
This is because non-switching dice behave as decaps for the switching die. However, 40 2D and 3D integrated systems J i ( s)'x'y Cdi 'x'y © 2007 IEEE Fig. 35 Simplified circuit model for 3D stacked system. Die n Die n-1 Die 1 Package Absolute Valuue of Power Nooise (mV) (a) W o r s t C a s e P e a k N o is e f o r T o p m o s t D ie ( S P I C E ) W o r s t C a s e P e a k N o is e f o r T o p m o s t D ie ( P h y s ic a l M o d e l) 180 160 140 0 2 4 6 8 10 T o ta l n u m b e r o f d ic e (b) Fig.
If only one die is switching, the noise is smaller than the single chip case (2-D case), because the switching die can use the decaps of those non-switching die in the 3D stacks. 37. 38. If the total number of die is increased and the noise levels of the topmost and bottommost levels are examined, it can be seen that when all die are switching the noise produced in a 3D integrated system is unacceptable when compared to a single chip case. This is especially true for the topmost die where the noise level changes dramatically (180 mV for the single die case as opposed to 790 mV for the 10 die case).
Coupled Data Communication Techniques for High-Performance and Low-Power Computing by Dr. Ron Ho, Dr. Robert Drost (auth.), Ron Ho, Robert Drost (eds.)