By Neil H. E. Weste, David Money Harris
For either introductory and complicated classes in VLSI layout, this authoritative, complete textbook is extremely obtainable to rookies, but bargains unprecedented breadth and intensity for more matured readers. The Fourth variation of CMOS VLSI layout: A Circuits and structures point of view provides wide and in-depth insurance of the total box of recent CMOS VLSI layout. The authors draw upon huge and lecture room adventure to introduce today’s so much complex and potent chip layout practices. They current generally up to date assurance of each key component of VLSI layout, and light up the most recent layout demanding situations with sixty five nm procedure examples. This publication includes unsurpassed circuit-level assurance, in addition to a wealthy set of difficulties and labored examples that offer deep useful perception to readers in any respect degrees.
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Additional info for CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition)
Of course, these estimates are oversimpliﬁcations of the complete design rules and a trial layout should be performed for truly critical cells. 18) and estimate the cell width and height. 47 shows a stick diagram. Counting horizontal and vertical pitches gives an estimated cell size of 40 by 48 Q. 6 Design Partitioning By this point, you know that MOS transistors behave as voltage-controlled switches. You know how to build logic gates out of transistors. And you know how transistors are fabricated and how to draw a layout that speciﬁes how transistors should be placed and connected together.
Instead, we can build noninverting functions from multiple stages of inverting gates. 23 shows several ways to build a 4-input AND gate from two levels of inverting static CMOS gates. Each design has different speed, size, and power trade-offs. 18 could be built with two AND gates, an OR gate, and an inverter. 18. Good CMOS logic designers exploit the efﬁciencies of compound gates rather than using large numbers of AND/OR gates. 25 shows symbols for a tristate buffer. When the enable input EN is 1, the output Y equals the input A, just as in an ordinary buffer.
18 CMOS compound gate for function Y = (A · B) + (C · D) This AOI22 gate can be used as a 2-input inverting multiplexer by connecting C = A as a select signal. Then, Y = B if C is 0, while Y = D if C is 1. 8 shows a way to improve this multiplexer design. 2 B Sketch a static CMOS gate computing Y = (A + B + C) · D. 19 shows such an OR-AND-INVERT-3-1 (OAI31) gate. The nMOS pull-down network pulls the output low if D is 1 and either A or B or C are 1, so D is in series with the parallel combination of A, B, and C.
CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition) by Neil H. E. Weste, David Money Harris