By Olivier Jamin
This booklet discusses the trade-offs thinking about designing direct RF digitization receivers for the radio frequency and electronic sign processing domain names. A system-level framework is built, quantifying the correct impairments of the sign processing chain, via a accomplished system-level research. exact concentration is given to noise research (thermal noise, quantization noise, saturation noise, signal-dependent noise), broadband non-linear distortion research, together with the effect of the sampling technique (low-pass, band-pass), research of time-interleaved ADC channel mismatches, sampling clock purity and electronic channel choice. The system-level framework defined is utilized to the layout of a cable multi-channel RF direct digitization receiver. An optimal RF sign conditioning, and a few algorithms (automatic achieve keep watch over loop, RF front-end amplitude equalization keep an eye on loop) are used to chill the necessities of a 2.7GHz 11-bit ADC.
A two-chip implementation is gifted, utilizing BiCMOS and 65nm CMOS approaches, including the block and system-level size effects. Readers will enjoy the thoughts provided, that are hugely aggressive, either when it comes to fee and RF functionality, whereas tremendously lowering strength consumption.
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3 Analog-to-Digital Conversion 21 ϕ1 φ1 sub-ADC TH sub-ADC in(t) Dig mux out(nT) sub-ADC TH φM sub-ADC ϕN Fig. 28 TH hierarchy In , a 40 GSps 6-bit ADC using 16 SAR ADCs is presented. In order to preserve the input bandwidth, the TH circuits are split into 2 banks of 8, driven through a 6-dB loss power splitter. In high-resolution ADCs, as the TH input capacitance increases (dictated by KT/C noise), only few TH units can be parallelized in order to preserve the input BW and minimize BW mismatches.
29. State of the art shows that CMOS processes gate scaling facilitates the increase of sampling rate of data conversion functions (ADCs, DACs). On the other hand, downward scaling of supply voltage in CMOS processes, required to compensate for the reduced oxide thickness, exacerbates the design of high-dynamic-range data converters. Obviously, modern CMOS processes allow massive integration of DSP functions, required for detecting and correcting analog impairments. E-03 10 20 30 40 50 60 70 80 90 100 SNDR [dB] Fig.
34 Direct conversion delta-sigma receiver I/Q imbalance (amplitude and phase) can degrade image rejection. Still, this image problem is reduced in a homodyne receiver since the image is one side of the received channel itself, as opposed to a heterodyne receiver where the channel lying at the image frequency can have much higher amplitude. In addition, I/Q digital calibration techniques can keep this effect under control . In case the homodyne receiver is fed with two closed RF channels (FRF1 ¼ FRF2 þε), second-order nonlinear distortion causes unwanted power at baseband (f ¼ ε) at the mixer input.
Broadband Direct RF Digitization Receivers by Olivier Jamin