By Gabriele Manganaro
Have to wake up to hurry speedy at the newest advances in excessive functionality information converters? wish support identifying the easiest structure on your program? With every thing you want to find out about the major new converter architectures, this advisor is for you. It provides uncomplicated rules, circuit and procedure layout thoughts and linked trade-offs, getting rid of long mathematical proofs and offering intuitive descriptions in advance. every thing from time-to-digital converters to comparator-based/zero-crossing ADCs is roofed and every subject is brought with a brief precis of the fundamental fundamentals. sensible examples describing genuine chips, in addition to vast comparability among architectural or circuit thoughts, ease structure choice and assist you lower layout time and engineering possibility. Trade-offs, benefits and drawbacks of every alternative are placed into point of view with a dialogue of destiny developments, displaying the place this box is heading, what's using it and what an important unanswered questions are.
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Additional info for Advanced data converters
Clearly, having a mix of analog and digital estimation and calibration can be optimal in many cases as well. Before completing this section we will briefly examine two important considerations associated with calibration in general. First of all, the use of calibration can be exploited to design faster, and possibly smaller, circuits. For example, if calibration can take care of correcting for mismatch of devices or for parameter spread then many circuits can be designed/optimized for much higher speed, selectively and appropriately using smaller devices with associated smaller parasitics.
G. f s > 100 MS/s) current-steering DACs only, many different FOMs are found in the literature, and a few of them will be briefly reported here. Some of the “randomness” in DACs’ FOMs originates from the fundamental question of what performance metric(s) can more broadly capture the value and the technical challenges of a given design when considering such a very diverse and wide application space. Furthermore, some of the performance parameters tend to vary much more, over frequency, than in ADCs.
The dashed line in Fig. 9 corresponds to σj ∼ 1 ps (rms). e. the actual conversion process) insofar as it relates only to sampling. A similar chart can be made for DACs as well. 3, it is hard to choose which metrics can be more encompassing for such a broad space of cases. A somewhat arbitrary choice has then been made in the chart shown in Fig. 10, where, similarly to what was done for the ADCs, many classic DAC architectures have been mapped into the BW–SFDR plane. It should also be remarked that the extent of the overlap between some of these architectures is, in actuality, greater than what is depicted.
Advanced data converters by Gabriele Manganaro